The 4004 was s 4-bit processor designed for calculators, and is different from x86 in almost every way. The index register is set to zero in case of overflow. If the accumulator content has more than one bit on, the accumulator will be set to 15 (to indicate error). Noncoml, did you really read the manual? A subsequent read, write, or I/O operation of the RAM will utilize this address. "There are also plenty of other oddities, like I/O ports on both RAM and ROM chips, dedicated instructions for e.g.
Execution of a return instruction (BBL) will cause the saved address to be pulled out of the stack, therefore, program control is transferred to the next sequential instruction after the last JMS. If JCN is located on words 254 and 255 of a ROM page, when JCN is executed and the condition is true, program control is transferred to the 8-bit address on the next page where JCN is located. MICROPROCESSOR 4-Bit Parallel CPU With 46 . Too bad my favorite 1802 instruction never caught on: Intel 4004 programming manual (1973) [pdf], https://en.wikichip.org/wiki/4-bit_architecture. From that, the x86 architecture developed. The ACC content and carry/link are unaffected. The program counter is unaffected; after FIN has been executed the next instruction in sequence will be addressed. Control transfer - conditional (limited to current ROM), unconditional, call subroutine and return from subroutine. The 4 bit content of the index register is unaffected. Arithmetic - add, subtract, increment, decrement. a) Although FIN is a 1-word instruction, its execution requires two memory cycles (21.6 psec). The content of the accumulator and carry/link are rotated left. The content of the accumulator is decremented by 1. The carry/link bit is unaffected. Perhaps you are confusing it with the 8008 which is related to the 8080 which is related to the 8086 which is related to the 80286, 80386, 80486, and so forth. The least significant position of the accumulator is set to the value of the carry/link. If the designated condition code is true, program control is transferred to the instruction located at the 8 bit address A2A2A2A2, A1A1A1A1 on the same page (ROM) where JCN is located. When JIN is located at the address (PH) 1111 1111 program control is transferred to the next page in sequence and not to the same page where the JIN instruction is located. I will try to regain my lost karma by upvoting a chip at the 32- or 64-bit level. The address in ROM or RAM is not cleared until the next SRC instruction is executed. Note that there is separate "program RAM" and "data RAM", the latter having a more complicated structure with the aforementioned status characters.
The 8 bit content of the 0 index register pair (0000) (0001) is sent out as an address in the same page where the FIN instruction is located. For example, I never knew what the "status characters" in the data RAM chips were for. "keyboard processing" but no AND or OR instruction (with horrifyingly long examples on how to implement them in this document), and some instruction names for seemingly straightforward things that are completely unintuitive.
The 4004 has weird instructions like KBP (Keyboard Process) to decode a calculator keyboard.
If the result is different from 0, program control is transferred to the instruction located at the 8 bit address A2A2A2A2, A1A1A1A1 on the same page (ROM) where the ISZ instruction is located. The origin of x86 is the Datapoint 2200, a desktop computer built from TTL chips. The program counter (address stack) is pushed down one level. The 4004 isn't even a von Neumann architecture; it has separate data and instruction memory. 4004 instruction set consists of 46 instructions: Data moving instructions. I'd say the 4004 has more in common with a PIC10 than it does x86. The content of the three least significant accumulator bits is transferred to the comand control register within the CPU. The accumulator and the carry/link are unaffected. One thing the 4004 and 8008 do have in common is a similar floor plan for the chips. This manual suggests to use them to store sign and exponent, or program RAM addresses. WR1 (Write accumulator into RAM status character 1), WR2 (Write accumulator into RAM status character 2), WR3 (Write accumulator into RAM status character 3). Program control transfers to the next instruction following the last jump to subroutine (JMS) instruction.
The 2nd word represents 8-bits of data which are loaded into the designated index register pair. The accumulator and carry/link are unaffected. But I can definitely see 4004 DNA in x86. A 4 bit datapath may seem very limiting, but note that 4-bit microcontrollers are still produced in massive quantities today, used in devices which you may not even be aware of as having a microcontroller: I had know idea they were still popular! The carry/linkis unaffected. The 4 bit content of designated index register is loaded into the accumulator. Especially the way the segregate RAM into banks reminds me a lot of the x86 segments with their direct and indirect addressing modes. To be honest I haven't dig into other CPU families, so maybe these were pretty common.
The content of the previously selected RAM main memory character is transferred to the accumulator. (The LSB bit of the accumulator appears on I/O0, pin 16, of the 4001). I think you're seeing patterns that aren't really there. It is a special kind of online community that downvotes someone for liking the idea of four-bit integrated circuits. The address of the next instruction in sequence following JMS (return address) is saved in the push down stack. The 8 bit content of the designated index register pair is loaded into the low order 8 positions of the program counter. The carry/link is unaffected. Other processors of that era (e.g. WRO (Write accumulator into RAM status character 0). Poor, neglected 80186, nobody ever remembers it... Hmm, I don't know. b) 2 word instruction with an 16-bit code and an execution time of 21.6 usec. The 4 bit content of the designated index register (RRRR) is loaded into accumulator. The 4004 isn't even a von Neumann architecture; it has separate data and instruction memory. Thanks.
This command is also used to designate a ROM for a subsequent ROM I/O port operation.
The 4 bit content of the designated index register is complemented (ones complement) and added to content of the accumulator with borrow and the result is stored in the accumulator. We've come a long way, but it is really cool how easy is to tell that it is the x86-64's ancestor. In the frame bellow is a simple examle of Intel 4004 microprocessor program - adding two 4bit numbers. The 4004 is not an ancestor of x86 even though the part numbers make it seem so. Specifically, the first 2 bits of the address designatea RAM chip; the second 2 bits designate 1 out of 4 registers within the chip; the last 4 bits designate 1 out of 16 4-bit main memory characters within the register. 6800, 6502, 8080) have very different layouts so it's not just coincidence. Given a 4001 with I/O coded with 2 inputs and 2 outputs, when RDR is executed the transfer is as shown below: WRM (Write accumulator into RAM character). The 4004 is so weird that it stands in a class of its own, for me.
I'm not sure how much of its instruction set came from Busicom, the company that the 4004 was made for, instead of from Intel engineers.
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